1. Field of the Invention
The present invention relates to system interfaces for backplane technology. More particularly, the present invention relates to bridges and switching systems for establishing transmission interfaces among circuit boards or cards installed in computing device backplanes. The system enables the insertion of a greater number of cards in a backplane topology than has heretofore been possible.
2. Description of the Prior Art
Standards have been established for the architecture of the hardware employed to enable the exchange of electrical signals among processing devices. The processing devices include integrated circuit systems built on and using printed circuit boards by an increasingly wide array of suppliers. The architecture standards ensure that the various devices will, in fact, be able to communicate with one another as well as with central processing units that control the operation of such peripheral devices. These peripherals include, but are not limited to, printer interfaces, video, audio, and graphics interfaces, memory, external communications interfaces, or any other sort of discrete device performing particular computer-related functions.
The circuit boards associated with the peripherals may be activated upon connection with a primary hardware board, often referred to as a motherboard. The motherboard establishes the interconnection of the central processing unit, power, memory structures, and a backplane bus. The backplane bus is a primary communication interface coupling line having connections to one or more slots or sockets in parallel into which the peripheral circuit boards may be inserted. The slots include physical connectors and input/output interfaces to establish reception and transmission of signals among all devices coupled to the motherboard through the backplane bus. It is the architecture of the backplane bus that establishes the interface architectures required for the peripheral boards so that communication can occur between all peripherals and the central processing unit in an organized manner.
Several communication hardware protocols have been developed, a number of which have been or are being phased out as being inadequate to support the faster signal exchange rates and increased bandwidth required by newer applications. One of the first such architecture protocols that remains in use on older motherboards is the Industry Standard Architecture (ISA). ISA is an expansion bus slot configuration that accepts plug-ins for peripherals including sound and video displays, for example. Earlier ISA slots were of 8-bit configuration but they are mainly 16-bit slots now. A modified version of ISA, Extended ISA (EISA) was developed to extend the bus capacity to 32-bit with essentially the same convention applied to the ISA backplane slot architecture. Unfortunately, it is designed to run at the relatively slow ISA rate of 8 MHz clocking. In today""s computing world, that is often too slow.
Although ISA had been the primary standard, the Peripheral Component Interconnect (PCI) bus is now the most frequently implemented interface architecture. Although it continues to replace ISA, that architecture will be used by peripherals designers for as long as computing devices including ISA slots remain in use. PCI provides a relatively high-speed data path (33 MHz) among connected boards. PCI Local Bus is an open architecture specification that allows applications designers greater freedom in interface formation. PCI provides xe2x80x9cplug and playxe2x80x9d capability in that any peripherals with PCI-based interfaces are automatically configured at start up and therefore generate little to no delay for the central processing unit to establish communication. One advantage of PCI is that it permits the sharing of IRQs. An IRQ (Interrupt ReQuest) signals the central processing unit that activity associated with a peripheral device has started or ended. Since motherboards are configured with only a limited number of IRQ lines, any interface architecture that requires dedicated IRQ lines is necessarily limited. Such is the case with ISA, but not with PCI. For that reason, PCI architecture is ordinarily the first choice.
While the PCI design is an improvement on ISA, it has a history of problems with edge connectors, poor thermal characteristics, and limited interface (input/outputxe2x80x94I/O) capability. In fact, PCI backplane configuration is limited to only four slots. That is due in part to the need to resolve signal reflections or noise at the board-to-backplane interface. Subsequent developments to double the clock rate to 66 MHZ and to increase the bus width accommodated some of the reflection problems, resulting in a doubling to eight of the number of available PCI slots. That improvement established a new slot architecture referred to as eXtended PCI (PCI-X) architecture. Unfortunately, while providing more slot availability, PCI-X continues to suffer from the same problems associated with PCI.
Because of interconnection limitations associated with the PCI architectures, there are limits on the number of peripheral devices that may be coupled together. Bridging together two PCI-based backplanes may increase slot capacity; however, that simply increases the size/number of the computer device required to establish desired functionality. It also introduces its own latency and transmission complications. As a result, the Personal Computer Industrial Computer Manufacturing Group (PICMG) developed a standard to address these problems with the PCI functionality. The PICMG combined the architecture of the Eurocard interface with a passive backplane (that is, no active devices to regulate signal propagation, only passive elements), and a high-quality, high-density pin-and-socket arrangement to make improvements. All motherboard components are hence moved from the now passive backplane to a Single Board Computer (SBC) card to be present in the system slot of the passive backplane. The relatively new connection architecture, identified as COMPACTPCI, a registered trademark of PCI Industrial computers manufacturers Group (hereinafter referred to a cPCI), improved the peripheral board-to-backplane impedance match, thereby reducing unwanted reflections at that interface. cPCI is designed to be a more robust interface connector to establish solid electrical connections.
The improvements established in cPCI generated the ability to provide eight PCI slots at a 33 MHz-lock rate. However, at higher clock rates the number of available slots is reduced because of the reflective wave signaling technology being used. Using reflected wave technology means the signal travels at half its intended amplitude until it reaches the end of the backplane where it doubles to its intended amplitude and propagates back down the backplane to its point of origin. This round trip delay physically limits the backplane to the number of slot connections it can have for a given clock frequency. The cPCI architecture at 66 MHz available in typical computing systems has thus been limited to five open slots.
What is needed is a backplane architecture and interface system that allows for a greater number of slots available for peripheral connections without increasing the footprint of the backplane. Further, what is needed is a backplane architecture and related system that expands the number of slots available without requiring bridging from one backplane to another. Yet further, what is needed is such a backplane architecture and related system that does not compromise the integrity and rate of signal reception and transmission. Still further, what is needed is such a backplane architecture and related system that may optionally be compatible with legacy interface architectures including, but not limited to, ISA.
It is an object of the present invention to provide a backplane architecture and interface system that provides for an increase in the number of slots available for peripheral connections without increasing the footprint of the backplane. It is also an object of the present invention to provide a backplane architecture and related system that expands the number of slots available without requiring bridging from one backplane to another. It is another object of the present invention to provide a backplane architecture and related system that does not compromise the integrity and rate of signal reception and transmission. Still further, it is an object of the present invention to provide a backplane architecture and related system that may optionally be compatible with legacy interface architectures including, but not limited to, ISA.
These and other objects are achieved in the present invention by establishing a backplane bus driver arrangement that produces incident wave switching rather than reflective wave switching. That is, the driver establishes a voltage swing or step that is of sufficient amplitude to ensure that all receivers coupled to the bus recognize that swing as a valid change of logic state on the first signal edge. Presently, much of the signal propagation associated with PCI architecture is generated at the board level through CMOS, TTL, and LVTTL drivers and receivers, and their equivalents. Those drivers/receivers generate voltage swings that exceed 1.5 volts in order to produce changes in logic state. When those swing requirements are combined with existing bus impedances related to the connector traces, and the variations in impedances associated with different load impedances, impedance mismatches result. That is particularly the case as increasingly faster switching rates are desired. Those faster switching rates further exacerbate the impedance mismatches, thereby increasing signal noise. The resultant noise must be accounted for so that there is no confusion on the bus. This is achieved by reducing the wave path defined by the bus traces so that the noise settles in time to provide a voltage on the bus that is sufficient to provide a clear logic signal to all receivers on the bus. The path reduction limits the number of connector slots on the motherboard.
The reflective wave propagation is a limit on the bandwidth of the existing motherboard architecture. Unfortunately, it is a common limitation since existing drivers/receivers requiring such reflections are in common commercial use. The present invention involves the application of driver circuitry that generates incident waves rather than reflective waves. One example of such circuitry is the Gunning Transceiver Logic Plus (GTLP) transceiver.
The function of the incident wave switching driver is to ensure a valid change of state on all receivers connected to a backplane bus on the first pass of a propagated transition. For that, the potential of the signal must be strong enough to generate a logic HIGH (VIH) on a rising edge and a logic LOW (VIL) on a falling edge as each of the connected receivers dictates. If the signal must reflect from the end of the backplane traces to reach a valid potential for signal transition, the driver does not produce incident wave switching. Without incident wave switching, the connector slots must be sufficiently close to the end of the bus to ensure that the reflections generate enough switching potential within a required propagation rate. Therefore, incident wave switching enables longer bus connections without sacrificing signal propagation rate.
The driving circuitry used to generate incident wave switching must be selected with the dynamic characteristics of the backplane in mind. Specifically, variations in capacitance, inductance, and resistance of the bus and the receiver connections affect whether that form of switching is achieved. That is, the driving circuitry must either overcome or balance that variability so that impedance mismatching does not occur, or that it does not generate signal reflection. That resolution of dynamic variability is achieved in the present invention through the selection of appropriate signal driving circuitry and the coupling of appropriate impedance devices between the driving circuitry, its power supply, the bus, and, if required, the individual receivers associated with the individual cards.
As indicated, the driver used in the present invention must be capable of generating incident wave switching. One type of circuit for doing so is described in pending U.S. patent application Ser. No. 09/132,595 of Oscar Freitas, filed Aug. 11, 1998, and assigned to a common assignee. The content of that application is incorporated herein by reference. One example of such a driver is the GTLP transceiver, such as model GTLP18T612 offered by Fairchild Semiconductor of South Portland, Me. This driver (transceiver) slows the signal transition enough to minimize noise significantly and therefore avoids reflections.
In addition to the introduction of an incident wave-switching driver, the present invention includes a fairly specific backplane layout to assist in minimizing impedance mismatches. Specifically, the stub impedance (impedance of the connectors for connecting a daughter card to the backplane bus), and backplane impedance. In general, the present invention shortens the connector stubs (thereby reducing their impedances), while maintaining the backplane impedance at or near its current typical value. The present invention relates to selecting appropriate values for those characteristics of the layout and coupling that with suitable incident wave driver technology to increase the number of slots available on a cPCI backplane or PCI/PCI-X motherboard layout without compromising signal integrity or throughput. It further includes resolution of appropriate signal clocking to minimize clock skew.
As earlier noted, most of the existing peripheral devices employ driver circuitry that generates reflective wave switching. The fabrication of such devices on cards containing such drivers is well defined and well established. For that reason, it would be difficult to conveniently convert those processes to substitute incident wave drivers that would be compatible with the backplane layout improvements described. The present invention includes an interface bridge or interposer that addresses that difficulty. Specifically, the present invention includes an interface circuit that translates the driver/receiver switching architecture associated with each daughter card into driver/receiver switching architecture that produces incident wave switching. For example, the interface circuit may be a TTL-to-GTLP converter that produces the signal swing required to present a valid VIH on a rising edge and a valid VIL on a falling edge during a first propagation on the backplane bus.
The present invention includes a new backplane layout. That combined with incident wave switching and an interface circuit to enable incident wave switching produce a decided advantage in the number of cPCI slots that may be supplied on a backplane without increasing the board footprint and without bridging between or among backplanes. These and other advantages of the present invention will become apparent upon review of the following detailed description, the accompanying drawings, and the appended claims.